MC9S12XD256MAL Datasheet, PDF (884/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.4.2.10 Port H
This port is associated with the SPI1, SPI2, SCI4, and SCI5. Port H pins PH[7:0] can be used for either
general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1
and SPI2 modules. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”.
Port H offers 8 I/O pins with edge triggered interrupt capability (Section 22.4.3, “Pin Interrupts”).
NOTE
Port H is not available in 80-pin packages.
22.4.2.11 Port J
This port is associated with the chip selects CS0, CS1, CS2 and CS3 as well as with CAN4, CAN0, IIC1,
IIC0, and SCI2. Port J pins PJ[7:4] and PJ[2:0] can be used for either general purpose I/O, or with the
CAN, IIC, or SCI subsystems. If IIC takes precedence the associated pins become IIC open-drain output
pins. The CAN4 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”.
Port J pins can be used with the routed CAN0 modules. Refer to Section 22.3.2.37, “Module Routing
Register (MODRR)”.
Port J offers 7 I/O pins with edge triggered interrupt capability (Section 22.4.3, “Pin Interrupts”).
NOTE
PJ[5,4,2] are not available in 112-pin packages. PJ[5,4,2,1,0] are not
available in 80-pin packages.
22.4.2.12 Port AD0
This port is associated with the ATD0. Port AD0 pins PAD07–PAD00 can be used for either general
purpose I/O, or with the ATD0 subsystem.
22.4.2.13 Port AD1
This port is associated with the ATD1. Port AD1 pins PAD23–PAD08 can be used for either general
purpose I/O, or with the ATD1 subsystem.
NOTE
PAD[23:16] are not available in 112-pin packages. PAD[23:08] are not
available in 80-pin packages.
MC9S12XDP512 Data Sheet, Rev. 2.21
886
Freescale Semiconductor