MC9S12XD256MAL Datasheet, PDF (152/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.16.2 Right Justified Result Data
7
6
5
4
3
2
1
R (10-BIT)
0
0
0
0
0
0
BIT 9 MSB
R (8-BIT)
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-20. Right Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
0
BIT 8
0
0
7
R (10-BIT) BIT 7
R (8-BIT) BIT 7 MSB
6
BIT 6
BIT 6
5
BIT 5
BIT 5
4
BIT 4
BIT 4
3
BIT 3
BIT 3
2
BIT 2
BIT 2
1
BIT 1
BIT 1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-21. Right Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
0
BIT 0
BIT 0
0
4.4 Functional Description
The ATD10B16C is structured in an analog and a digital sub-block.
4.4.1 Analog Sub-block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V_DDA and V_SSA allow to isolate noise of other MCU circuitry from the analog sub-block.
4.4.1.1 Sample and Hold Machine
The sample and hold (S/H) machine accepts analog signals from the external world and stores them as
capacitor charge on a storage node.
The sample process uses a two stage approach. During the first stage, the sample amplifier is used to
quickly charge the storage node.The second stage connects the input directly to the storage node to
complete the sample for high accuracy.
When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue
drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks
and the analog power consumption.
The input analog signals are unipolar and must fall within the potential range of V_SSA to VDDA.
MC9S12XDP512 Data Sheet, Rev. 2.21
152
Freescale Semiconductor