MC9S12XD256MAL Datasheet, PDF (520/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 12 Serial Peripheral Interface (S12SPIV4)
12.3.2.1 SPI Control Register 1 (SPICR1)
R
W
Reset
7
SPIE
0
Read: Anytime
Write: Anytime
6
SPE
5
SPTIE
4
MSTR
3
CPOL
2
CPHA
0
0
0
0
1
Figure 12-3. SPI Control Register 1 (SPICR1)
1
SSOE
0
0
LSBFE
0
Table 12-1. SPICR1 Field Descriptions
Field
7
SPIE
6
SPE
5
SPTIE
4
MSTR
3
CPOL
2
CPHA
1
SSOE
0
LSBFE
Description
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
0 SPI interrupts disabled.
1 SPI interrupts enabled.
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.
Switching the SPI from master to slave or vice versa forces the SPI system into idle state.
0 SPI is in slave mode.
1 SPI is in master mode.
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Active-high clocks selected. In idle state SCK is low.
1 Active-low clocks selected. In idle state SCK is high.
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will
abort a transmission in progress and force the SPI system into idle state.
0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock.
1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock.
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in Table 12-2. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
MC9S12XDP512 Data Sheet, Rev. 2.21
520
Freescale Semiconductor