MC9S12XD256MAL Datasheet, PDF (870/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.59 Port J Polarity Select Register (PPSJ)
R
W
Reset
7
PPSJ7
0
6
5
4
3
2
0
PPSJ6
PPSJ5
PPSJ4
PPSJ2
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-61. Port J Polarity Select Register (PPSJ)
1
PPSJ1
0
0
PPSJ0
0
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting
a pull-up or pull-down device if enabled.
Table 22-55. PPSJ Field Descriptions
Field
Description
7–0
PPSJ[7:4]
PPSJ[2:0]
Polarity Select Port J
0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register.
A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as general purpose input or as IIC port.
1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register.
A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as input.
22.3.2.60 Port J Interrupt Enable Register (PIEJ)
R
W
Reset
7
PIEJ7
0
6
5
4
3
2
0
PIEJ6
PIEJ5
PIEJ4
PIEJ2
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-62. Port J Interrupt Enable Register (PIEJ)
1
PIEJ1
0
0
PIEJ0
0
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port J.
Table 22-56. PIEJ Field Descriptions
Field
Description
7–0
PIEJ[7:4]
PIEJ[2:0]
Interrupt Enable Port J
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
MC9S12XDP512 Data Sheet, Rev. 2.21
872
Freescale Semiconductor