MC9S12XD256MAL Datasheet, PDF (841/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.22 Port T Polarity Select Register (PPST)
R
W
Reset
7
PPST7
0
6
PPST6
5
PPST5
4
PPST4
3
PPST3
2
PPST2
0
0
0
0
0
Figure 22-24. Port T Polarity Select Register (PPST)
1
PPST1
0
0
PPST0
0
Read: Anytime.
Write: Anytime.
This register selects whether a pull-down or a pull-up device is connected to the pin.
Table 22-26. PPST Field Descriptions
Field
Description
7–0
PPST[7:0]
Pull Select Port T
0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT
and if the port is used as input.
1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT
and if the port is used as input.
22.3.2.23 Port S Data Register (PTS)
R
W
SCI/SPI
Reset
7
PTS7
SS0
0
6
PTS6
5
PTS5
4
PTS4
3
PTS3
2
PTS2
SCK0
0
MOSI0
MISO0
TXD1
RXD1
0
0
0
0
Figure 22-25. Port S Data Register (PTS)
1
PTS1
TXD0
0
0
PTS0
RXD0
0
Read: Anytime.
Write: Anytime.
Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status
bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be
used as general purpose I/O.
Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and
1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and
0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with
the SCI, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
843