MC9S12XD256MAL Datasheet, PDF (562/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register
(VREGAPIRH / VREGAPIRL)
The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous
periodical interrupt rate.
R
W
Reset
7
6
5
4
3
2
1
0
0
0
0
APIR11
APIR10
APIR9
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-6. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH)
0
APIR8
0
R
W
Reset
7
APIR7
6
APIR6
5
APIR5
4
APIR4
3
APIR3
2
APIR2
1
APIR1
0
0
0
0
0
0
0
Figure 14-7. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL)
0
APIR0
0
Table 14-7. VREGAPIRH / VREGAPIRL Field Descriptions
Field
Description
11-0
Autonomous Periodical Interrupt Rate Bits — These bits define the timeout period of the API. See Table 14-8
APIR[11:0] for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of VREGAPICL
register.
MC9S12XDP512 Data Sheet, Rev. 2.21
562
Freescale Semiconductor