MC9S12XD256MAL Datasheet, PDF (701/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
Table 19-14. CDCM Encoding
CDCM
00
01
10
11
Description
Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
Match2 mapped to comparator C/D inside range....... Match3 disabled.
Match2 mapped to comparator C/D outside range....... Match3 disabled.
Reserved
ABCM
00
01
10
11
Table 19-15. ABCM Encoding
Description
Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
Match 0 mapped to comparator A/B inside range....... Match1 disabled.
Match 0 mapped to comparator A/B outside range....... Match1 disabled.
Reserved
19.3.1.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)
0x0024
15
14
13
12
11
10
R
Bit 15
14
13
12
11
10
W
Reset
X
X
X
X
X
X
9
8
9
Bit 8
X
X
Figure 19-7. Debug Trace Buffer Register (DBGTBH)
0x0025
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
X
X
X
X
X
X
X
X
Figure 19-8. Debug Trace Buffer Register (DBGTBL)
Read: Anytime when unlocked and not secured and not armed.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents
Table 19-16. DBGTB Field Descriptions
Field
15–0
Bit[15:0]
Description
Trace Buffer Data Bits — The trace buffer register is a window through which the 64-bit wide data lines of the
trace buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer
which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent
reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when
the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned
access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace
buffer address. The same is true for word reads while the debugger is armed. System resets do not affect the
trace buffer contents. The POR state is undefined.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
703