MC9S12XD256MAL Datasheet, PDF (1018/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Table 24-46. PIFH Field Descriptions
Field
Description
7–0
PIFH[7:0]
Interrupt Flags Port H
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a logic level “1” clears the associated flag.
24.0.5.50 Port J Data Register (PTJ)
7
6
5
4
3
2
1
0
R
0
0
0
0
PTJ7
PTJ6
PTJ1
PTJ0
W
CAN4 TXCAN4 RXCAN4
IIC0 SCL0
SDA0
Routed
CAN0
TXCAN0
RXCAN0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-52. Port J Data Register (PTJ)
Read: Anytime.
Write: Anytime.
Port J pins 7–6 are associated with the CAN4, IIC0, the routed CAN0 modules. These pins can be used as
general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read except for bits 5-2 which read “0”.
Table 24-47. PTJ Field Descriptions
Field
7–6
PJ[7:6]
Description
The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC0, the routed CAN0 and the general
purpose I/O function if the CAN4 module is enabled.
The IIC0 function (SCL0 and SDA0) takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured
as open drain outputs. Refer to IIC section for details.
The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if
the routed CAN0 module is enabled. Refer to MSCAN section for details.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor