MC9S12XD256MAL Datasheet, PDF (1015/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

This register always reads back the buffered state of the associated pins. This can also be used to
detect overload or short circuit conditions on output pins.
24.0.5.44 Port H Data Direction Register (DDRH)
7
R
DDRH7
W
6
DDRH6
5
DDRH5
4
DDRH4
3
DDRH3
2
DDRH2
1
DDRH1
0
DDRH0
Reset
0
0
0
0
0
0
0
0
Figure 24-46. Port H Data Direction Register (DDRH)
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
If the associated routed SPI module is enabled this register has no effect on the pins.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral
modules are disabled.
Table 24-41. DDRH Field Descriptions
Field
Description
7–0
DDRH[7:0]
Data Direction Port H
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTH or PTIH registers, when changing the DDRH register.
24.0.5.45 Port H Reduced Drive Register (RDRH)
R
W
Reset
7
RDRH7
0
6
RDRH6
5
RDRH5
4
RDRH4
3
RDRH3
2
RDRH2
0
0
0
0
0
Figure 24-47. Port H Reduced Drive Register (RDRH)
1
RDRH1
0
0
RDRH0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each Port H output pin as either full or reduced. If the
port is used as input this bit is ignored.