MC9S12XD256MAL Datasheet, PDF (623/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.3.2.5 MMC Control Register (MMCCTL1)
Address: 0x0013 PRR
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
0
EROMON
0
EROMCTL
Figure 17-10. MMC Control Register (MMCCTL1)
1
ROMHM
0
0
ROMON
ROMCTL
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.
Write: Refer to each bit description. In emulation modes write operations will also be directed to the
external bus.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Table 17-9. MMCCTL1 Field Descriptions
Field
Description
2
EROMON
1
ROMHM
0
ROMON
Enables emulated Flash or ROM memory in the memory map
Write: Never
0 Disables the emulated Flash or ROM in the memory map.
1 Enables the emulated Flash or ROM in the memory map.
FLASH or ROM only in higher Half of Memory Map
Write: Once in normal and emulation modes and anytime in special modes
0 The fixed page of Flash or ROM can be accessed in the lower half of the memory map. Accesses to
$4000–$7FFF will be mapped to $7F_4000-$7F_7FFF in the global memory space.
1 Disables access to the Flash or ROM in the lower half of the memory map.These physical locations of the
Flash or ROM can still be accessed through the program page window. Accesses to $4000–$7FFF will be
mapped to $14_4000-$14_7FFF in the global memory space (external access).
Enable FLASH or ROM in the memory map
Write: Once in normal and emulation modes and anytime in special modes
0 Disables the Flash or ROM from the memory map.
1 Enables the Flash or ROM in the memory map.
EROMON and ROMON control the visibility of the Flash in the memory map for CPU or BDM (not for
XGATE). Both local and global memory maps are affected.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
623