MC9S12XD256MAL Datasheet, PDF (792/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 21 External Bus Interface (S12XEBIV2)
21.4 Functional Description
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
21.4.1 Operating Modes and External Bus Properties
A summary of the external bus interface functions for each operating mode is shown in Table 21-7.
Table 21-7. Summary of Functions
Properties
(if Enabled)
Single-Chip Modes
Normal
Single-Chip
Special
Single-Chip
Normal
Expanded
Expanded Modes
Emulation
Single-Chip
Emulation
Expanded
Special
Test
PRR access¹
2 cycles
read internal
write internal
Timing Properties
2 cycles
read internal
write internal
2 cycles
read internal
write internal
2 cycles
read external
write int & ext
2 cycles
read external
write int & ext
Internal access
—
visible externally
—
—
1 cycle
1 cycle
External
—
address access
and
unimplemented area
access²
—
Max. of 2 to 9
1 cycle
Max. of 2 to 9
programmed
programmed
cycles
cycles
or n cycles of
ext. wait³
or n cycles of
ext. wait³
Flash area
—
—
—
1 cycle
1 cycle
address access⁴
Signal Properties
Bus signals
—
—
ADDR[22:1] ADDR[22:20]/A ADDR[22:20]/A
DATA[15:0]
CC[2:0]
CC[2:0]
ADDR[19:16]/ ADDR[19:16]/
IQSTAT[3:0] IQSTAT[3:0]
ADDR[15:0]/ ADDR[15:0]/
IVD[15:0]
IVD[15:0]
DATA[15:0]
DATA[15:0]
Data select signals
—
(if 16-bit data bus)
—
UDS
ADDR0
ADDR0
LDS
LSTRB
LSTRB
Data direction signals
—
—
RE
R/W
R/W
WE
External wait
—
feature
—
EWAIT
—
EWAIT
Reduced input
—
threshold enabled on
—
Refer to
DATA[15:0]
DATA[15:0]
Table 21-3
EWAIT
EWAIT
1 _{Incl. S12X_EBI registers}
2 _{Refer to S12X_MMC section.}
3 _{If EWAITE = 1, the minimum number of external bus cycles is 3.}
4 _{Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).}
2 cycles
read internal
write internal
1 cycle
1 cycle
1 cycle
ADDR[22:0]
DATA[15:0]
ADDR0
LSTRB
R/W
—
Refer to
Table 21-3
MC9S12XDP512 Data Sheet, Rev. 2.21
794
Freescale Semiconductor