MC9S12XD256MAL Datasheet, PDF (107/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 2 Clocks and Reset Generator (S12CRGV6)
CME
0
1
1
1
SCME
X
0
1
1
Table 2-12. Outcome of Clock Loss in Wait Mode
SCMIE
CRG Actions
X
Clock failure -->
No action, clock loss not detected.
X
Clock failure -->
CRG performs Clock Monitor Reset immediately
Clock failure -->
Scenario 1: OSCCLK recovers prior to exiting wait mode.
– MCU remains in wait mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag.
Some time later OSCCLK recovers.
– CM no longer indicates a failure,
– 4096 OSCCLK cycles later clock quality check indicates clock o.k.,
– SCM deactivated,
– PLL disabled depending on PLLWAI,
– VREG remains enabled (never gets disabled in wait mode).
– MCU remains in wait mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit wait mode using OSCCLK as system clock (SYSCLK),
0
– Continue normal operation.
or an External Reset is applied.
– Exit wait mode using OSCCLK as system clock,
– Start reset sequence.
Scenario 2: OSCCLK does not recover prior to exiting wait mode.
– MCU remains in wait mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start clock quality check,
– Set SCMIF interrupt flag,
– Keep performing clock quality checks (could continue infinitely) while in wait mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit wait mode in SCM using PLL clock (f_SCM) as system clock,
– Continue to perform additional clock quality checks until OSCCLK is o.k. again.
or an External RESET is applied.
– Exit wait mode in SCM using PLL clock (f_SCM) as system clock,
– Start reset sequence,
– Continue to perform additional clock quality checks until OSCCLKis o.k.again.
Clock failure -->
– VREG enabled,
– PLL enabled,
– SCM activated,
1
– Start clock quality check,
– SCMIF set.
SCMIF generates self clock mode wakeup interrupt.
– Exit wait mode in SCM using PLL clock (f_SCM) as system clock,
– Continue to perform a additional clock quality checks until OSCCLK is o.k. again.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
107