MC9S12XD256MAL Datasheet, PDF (150/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.15 Port Data Register 1 (PORTAD1)
The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs
AN7-0.
R
W
Reset
Pin
Function
7
PTAD7
1
AN 7
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
1
1
1
1
1
AN6
AN5
AN4
AN3
AN2
= Unimplemented or Reserved
Figure 4-17. Port Data Register 1 (PORTAD1)
Read: Anytime
Write: Anytime, no effect
The A/D input channels may be used for general-purpose digital input.
Table 4-26. PORTAD1 Field Descriptions
1
PTAD1
1
AN1
0
PTAD0
1
AN0
Field
7:0
PTAD[7:8]
Description
A/D Channel x (ANx) Digital Input Bits — If the digital input buffer on the ANx pin is enabled (IENx=1) or
channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the
logic level on ANx pin (signal potentials not meeting V_IL or V_IH specifications will have an indeterminate value)).
If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns
a “1”.
Reset sets all PORTAD1 bits to “1”.
MC9S12XDP512 Data Sheet, Rev. 2.21
150
Freescale Semiconductor