MC9S12XD256MAL Datasheet, PDF (279/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

STW
Store Word to Memory
Chapter 6 XGATE (S12XGATEV2)
STW
Operation
RS ⇒ M[RB, #OFFS5]
RS ⇒ M[RB, RI]
RS ⇒ M[RB, RI]; RI+2 ⇒ RI;
RI–2 ⇒ RI; RS ⇒ M[RB, RI]¹
Stores the content of register RS to memory.
CCR Effects
NZVC
————
N: Not affected.
Z: Not affected.
V: Not affected.
C: Not affected.
Code and CPU Cycles
Source Form
STW RS, (RB, #OFFS5)
STW RS, (RB, RI)
STW RS, (RB, RI+)
STW RS, (RB, -RI)
Address
Mode
IDO5
IDR
IDR+
-IDR
01011
01111
01111
01111
Machine Code
RS
RB
RS
RB
RS
RB
RS
RB
Cycles
OFFS5
PW
RI 0 0 PW
RI 0 1 PW
RI 1 0 PW
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
register is written to the memory: RS ⇒ M[RB, RS–2]; RS–2 ⇒ RS
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
279