MC9S12XD256MAL Datasheet, PDF (933/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This also can be used to
detect overload or short circuit conditions on output pins.
23.0.5.25 Port S Data Direction Register (DDRS)
R
W
Reset
7
DDRS7
0
6
DDRS6
5
DDRS5
4
DDRS4
3
DDRS3
2
DDRS2
0
0
0
0
0
Figure 23-27. Port S Data Direction Register (DDRS)
1
DDRS1
0
0
DDRS0
0
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins.
The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if
the SCI receive channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is
disabled.
Table 23-27. DDRS Field Descriptions
Field
Description
7–0
DDRS[7:0]
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTS or PTIS registers, when changing the DDRS register.
23.0.5.26 Port S Reduced Drive Register (RDRS)
R
W
Reset
7
RDRS7
0
Read: Anytime.
Write: Anytime.
6
RDRS6
5
RDRS5
4
RDRS4
3
RDRS3
2
RDRS2
0
0
0
0
0
Figure 23-28. Port S Reduced Drive Register (RDRS)
1
RDRS1
0
0
RDRS0
0