MC9S12XD256MAL Datasheet, PDF (1215/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
29.4.2.2.1 Data Compress Operation
The Flash module contains a 16-bit multiple-input signature register (MISR) to generate a 16-bit signature
based on selected Flash array data. The final 16-bit signature, found in the FDATA registers after the data
compress operation has completed, is based on the following logic equation which is executed on every
data compression cycle during the operation:
MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0]
Eqn. 29-1
where MISR is the content of the internal signature register and DATA is the data to be compressed as
shown in Figure 29-25.
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[15]
+ DQ + DQ + DQ + DQ + DQ + DQ
...
M0
M1
M2
M3
M4
M5
>
>
>
>
>
>
+ DQ
M15
>
+
+ = Exclusive-OR
MISR[15:0] = Q[15:0]
+
+
Figure 29-25. 16-Bit MISR Diagram
During the data compress operation, the following steps are executed:
1. MISR is reset to 0xFFFF.
2. Initialized DATA equal to 0xFFFF is compressed into the MISR which results in the MISR
containing 0x0001.
3. DATA equal to the selected Flash array data range is read and compressed into the MISR with
addresses incrementing.
4. DATA equal to the selected Flash array data range is read and compressed into the MISR with
addresses decrementing.
5. DATA equal to the contents of the MISR is compressed into the same MISR.
6. The contents of the MISR are written to the FDATA registers.
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
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