MC9S12XD256MAL Datasheet, PDF (872/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0)
7
R
DDR1AD07
W
6
DDR1AD06
5
DDR1AD05
4
DDR1AD04
3
DDR1AD03
2
DDR1AD02
1
DDR1AD01
0
DDR1AD00
Reset
0
0
0
0
0
0
0
0
Figure 22-65. Port AD0 Data Direction Register 1 (DDR1AD0)
Read: Anytime.
Write: Anytime.
This register configures pins PAD[07:00] as either input or output.
Table 22-58. DDR1AD0 Field Descriptions
Field
Description
7–0
DDR1AD0[7:0]
Data Direction Port AD0 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
read on PTAD01 register, when changing the DDR1AD0 register.
Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to
be set to logic level “1”.
MC9S12XDP512 Data Sheet, Rev. 2.21
874
Freescale Semiconductor