MC9S12XD256MAL Datasheet, PDF (178/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.11 ATD Input Enable Register (ATDDIEN)
R
W
Reset
7
IEN7
0
Read: Anytime
6
IEN6
5
IEN5
4
IEN4
3
IEN3
2
IEN2
0
0
0
0
0
Figure 5-13. ATD Input Enable Register (ATDDIEN)
1
IEN1
0
0
IEN0
0
Write: Anytime
Table 5-21. ATDDIEN Field Descriptions
Field
7–0
IEN[7:0]
Description
ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from
the analog input pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
5.3.2.12 Port Data Register (PORTAD)
The data port associated with the ATD can be configured as general-purpose I/O or input only, as specified
in the device overview. The port pins are shared with the analog A/D inputs AN7–0.
R
W
Reset
Pin
Function
7
PTAD7
1
AN7
Read: Anytime
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
1
1
1
1
1
AN6
AN5
AN4
AN3
AN2
= Unimplemented or Reserved
Figure 5-14. Port Data Register (PORTAD)
1
PTAD1
1
AN1
0
PTAD0
1
AN0
Write: Anytime, no effect
The A/D input channels may be used for general purpose digital input.
Table 5-22. PORTAD Field Descriptions
Field
7–0
PTAD[7:0]
Description
A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled
(IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2–0] = x,ETRIGSEL = 0) read
returns the logic level on ANx pin (signal potentials not meeting V_IL or V_IH specifications will have an
indeterminate value).
If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns
a “1”.
Reset sets all PORTAD0 bits to “1”.
MC9S12XDP512 Data Sheet, Rev. 2.21
178
Freescale Semiconductor