MC9S12XD256MAL Datasheet, PDF (1020/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.53 Port J Reduced Drive Register (RDRJ)
R
W
Reset
7
RDRJ7
0
6
5
4
3
2
0
0
0
0
RDRJ6
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-55. Port J Reduced Drive Register (RDRJ)
1
RDRJ1
0
0
RDRJ0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 24-49. RDRJ Field Descriptions
Field
Description
7–0
Reduced Drive Port J
RDRJ[7:6] 0 Full drive strength at output.
RDRJ[1:0] 1 Associated pin drives at about 1/6 of the full drive strength.
24.0.5.54 Port J Pull Device Enable Register (PERJ)
7
6
5
4
3
2
1
0
R
0
0
0
0
PERJ7
PERJ6
PERJ1
PERJ0
W
Reset
1
1
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 24-56. Port J Pull Device Enable Register (PERJ)
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or
as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up
device is enabled.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor