MC9S12XD256MAL Datasheet, PDF (120/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 3 Pierce Oscillator (S12XOSCLCPV1)
3.1.3 Block Diagram
Figure 3-1 shows a block diagram of the XOSC.
Clock
Monitor
Monitor_Failure
OSCCLK
Peak
Detector
Gain Control
V_DDPLL = 2.5 V
EXTAL
Rf
XTAL
Figure 3-1. XOSC Block Diagram
3.2 External Signal Description
This section lists and describes the signals that connect off chip
3.2.1 V_DDPLL and V_SSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (V_DDPLL) and ground (V_SSPLL) for the XOSC circuitry. This
allows the supply voltage to the XOSC to be independently bypassed.
3.2.2 EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal
clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier.
XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived from the
MC9S12XDP512 Data Sheet, Rev. 2.21
120
Freescale Semiconductor