MC9S12XD256MAL Datasheet, PDF (1276/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
In Figure A-10 the timing diagram for slave mode with transmission format CPHA = 1 is depicted.
SS
(Input)
SCK
(CPOL = 0)
(Input)
SCK
(CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
1
2
12
4
4
12
See
Note
9
Slave MSB OUT
7
5
6
MSB IN
11
Bit 6 . . . 1
Bit 6 . . . 1
3
13
13
8
Slave LSB OUT
LSB IN
NOTE: Not defined
Figure A-10. SPI Slave Timing (CPHA = 1)
In Table A-27 the timing characteristics for slave mode are listed.
Table A-27. SPI Slave Mode Timing Characteristics
Num C
Characteristic
Symbol
Min
1
D SCK frequency
f_sck
DC
1
D SCK period
t_sck
4
2
D Enable lead time
t_lead
4
3
D Enable lag time
t_lag
4
4
D Clock (SCK) high or low time
t_wsck
4
5
D Data setup time (inputs)
t_su
8
6
D Data hold time (inputs)
t_hi
8
7
D Slave access time (time to data active)
t_a
—
8
D Slave MISO disable time
t_dis
—
9
D Data valid after SCK edge
t_vsck
—
10
D Data valid after SS fall
t_vss
—
11
D Data hold time (outputs)
t_ho
20
12
D Rise and fall time inputs
t_rfi
—
13
D Rise and fall time outputs
t_rfo
—
1 _{0.5 tbus added due to internal synchronization delay}
Typ
Max
Unit
—
1/4
f_bus
—
∞
t_bus
—
—
t_bus
—
—
t_bus
—
—
t_bus
—
—
ns
—
—
ns
—
20
ns
—
22
ns
—
29 + 0.5 ⋅ t_bus1
ns
—
29 + 0.5 ⋅ t_bus1
ns
—
—
ns
—
8
ns
—
8
ns
1278
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor