MC9S12XD256MAL Datasheet, PDF (861/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.48 Port H Data Direction Register (DDRH)
R
W
Reset
7
DDRH7
0
6
DDRH6
5
DDRH5
4
DDRH4
3
DDRH3
2
DDRH2
0
0
0
0
0
Figure 22-50. Port H Data Direction Register (DDRH)
1
DDRH1
0
0
DDRH0
0
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
If the associated SCI channel or routed SPI module is enabled this register has no effect on the pins.
The SCI forces the I/O state to be an output for each port line associated with an enabled output (TXD5,
TXD4). It also forces the I/O state to be an input for each port line associated with an enabled input (RXD5,
RXD4). In those cases the data direction bits will not change.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral modules are
disabled.
Table 22-45. DDRH Field Descriptions
Field
Description
7–0
DDRH[7:0]
Data Direction Port H
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTH or PTIH registers, when changing the DDRH register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
863