MC9S12XD256MAL Datasheet, PDF (219/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
ADDL
Add Immediate 8 bit Constant
(Low Byte)
ADDL
Operation
RD + $00:IMM8 ⇒ RD
Adds the content of register RD and an unsigned immediate 8 bit constant using binary addition and stores
the result in the destination register RD. This instruction must be used first for a 16 bit immediate addition
in conjunction with the ADDH instruction.
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise.
RD[15]_old & RD[15]_new
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RD[15]_old & RD[15]_new
Code and CPU Cycles
Source Form
ADDL RD, #IMM8
Address
Mode
IMM8
11100
Machine Code
RD
IMM8
Cycles
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
219