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MC9S12XD256MAL Datasheet, PDF (171/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.5 ATD Control Register 4 (ATDCTL4)
This register selects the conversion clock frequency, the length of the second phase of the sample time and
the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current
conversion sequence but will not start a new sequence.
R
W
Reset
7
SRES8
0
6
SMP1
5
SMP0
4
PRS4
3
PRS3
2
PRS2
0
0
0
0
1
Figure 5-7. ATD Control Register 4 (ATDCTL4)
1
PRS1
0
0
PRS0
1
Read: Anytime
Write: Anytime
Table 5-10. ATDCTL4 Field Descriptions
Field
7
SRES8
6â5
SMP[1:0]
4â0
PRS[4:0]
Description
A/D Resolution Select â This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The
A/D converter has an accuracy of 10 bits; however, if low resolution is required, the conversion can be speeded
up by selecting 8-bit resolution.
0 10-bit resolution
8-bit resolution
Sample Time Select â These two bits select the length of the second phase of the sample time in units of
ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler
value (bits PRS4â0). The sample time consists of two phases. The ï¬rst phase is two ATD conversion clock
cycles long and transfers the sample quickly (via the buffer ampliï¬er) onto the A/D machineâs storage node.
The second phase attaches the external analog signal directly to the storage node for ï¬nal charging and high
accuracy. Table 5-11 lists the lengths available for the second sample phase.
ATD Clock Prescaler â These 5 bits are the binary value prescaler value PRS. The ATD conversion clock
frequency is calculated as follows:
ATDclock = [---B[---P-u---R-s----CS----l-+-o----c1----k]---] Ã 0.5
Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler
value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12.
Table 5-12 illustrates the divide-by operation and the appropriate range of the bus clock.
SMP1
0
0
1
1
Table 5-11. Sample Time Select
SMP0
0
1
0
1
Length of 2nd Phase of Sample Time
2 A/D conversion clock periods
4 A/D conversion clock periods
8 A/D conversion clock periods
16 A/D conversion clock periods
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
171
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