MC9S12XD256MAL Datasheet, PDF (1050/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1)
then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the
optimum target by:
(200 – 182) ⁄ 200 × 100 = 9%
CAUTION
Program and erase command execution time will increase proportionally
with the period of EECLK. Because of the impact of clock synchronization
on the accuracy of the functional timings, programming or erasing the
EEPROM memory cannot be performed if the bus clock runs at less than 1
MHz. Programming or erasing the EEPROM memory with EECLK < 150
kHz should be avoided. Setting ECLKDIV to a value such that EECLK <
150 kHz can destroy the EEPROM memory due to overstress. Setting
ECLKDIV to a value such that (1/EECLK+Tbus) < 5 µs can result in
incomplete programming or erasure of the EEPROM memory cells.
If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is 0, the
ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written
to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR
flag in the ESTAT register will set.
1052
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor