MC9S12XD256MAL Datasheet, PDF (921/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Table 23-8. PORTC Field Descriptions
Field
7–0
PC[7:0]
Description
Port C — Port C pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.
23.0.5.6 Port D Data Register (PORTD)
7
R
PD7
W
6
PD6
5
PD5
4
PD4
3
PD3
2
PD2
1
PD1
0
PD0
Reset
0
0
0
0
0
0
0
0
Figure 23-8. Port D Data Register (PORTD)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 23-9. PORTD Field Descriptions
Field
7–0
PD[7:0]
Description
Port D — Port D pins 7–0. — If the data direction bits of the associated I/O pins are set to logic level “1”, a read
returns the value of the port register, otherwise the buffered pin input state is read.
23.0.5.7 Port C Data Direction Register (DDRC)
7
R
DDRC7
W
6
DDRC6
5
DDRC5
4
DDRC4
3
DDRC3
2
DDRC2
1
DDRC1
0
DDRC0
Reset
0
0
0
0
0
0
0
0
Figure 23-9. Port C Data Direction Register (DDRC)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 23-10. DDRC Field Descriptions
Field
Description
7–0
DDRC[7:0]
Data Direction Port C — This register controls the data direction for port C. DDRC determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTC after changing the DDRC register.