MC9S12XD256MAL Datasheet, PDF (116/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 2 Clocks and Reset Generator (S12CRGV6)
RESET
Clock Quality Check
(no Self-Clock Mode)
)(
Internal POR
Internal RESET
)(
128 SYSCLK
)(
64 SYSCLK
Figure 2-26. RESET Pin Tied to V_DD (by a pull-up resistor)
RESET
Clock Quality Check
(no Self Clock Mode)
)(
Internal POR
Internal RESET
)(
128 SYSCLK
)(
64 SYSCLK
Figure 2-27. RESET Pin Held Low Externally
2.6 Interrupts
The interrupts/reset vectors requested by the CRG are listed in Table 2-16. Refer to MCU specification for
related vector addresses and priorities.
Table 2-16. CRG Interrupt Vectors
Interrupt Source
Real time interrupt
LOCK interrupt
SCM interrupt
CCR
Mask
I bit
I bit
I bit
Local Enable
CRGINT (RTIE)
CRGINT (LOCKIE)
CRGINT (SCMIE)
2.6.1 Real Time Interrupt
The CRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are
locally disabled by setting the RTIE bit to 0. The real time interrupt flag (RTIF) is set to1 when a timeout
occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during pseudo stop mode if the PRE bit is set to 1. This feature can be used for
periodic wakeup from pseudo stop if the RTI interrupt is enabled.
MC9S12XDP512 Data Sheet, Rev. 2.21
116
Freescale Semiconductor