MC9S12XD256MAL Datasheet, PDF (250/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
CMPL
Compare Immediate 8 bit Constant
(Low Byte)
CMPL
Operation
RS.L – IMM8 ⇒ NONE, only condition code flags get updated
Subtracts the 8 bit constant IMM8 contained in the instruction code from the low byte of the source register
RS.L using binary subtraction and updates the condition code register accordingly.
Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers
can be performed by using the subtract instruction with R0 as destination register.
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 7 of the result is set; cleared otherwise.
Z: Set if the 8 bit result is $00; cleared otherwise.
V: Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise.
RS[7] & IMM8[7] & result[7] | RS[7] & IMM8[7] & result[7]
C: Set if there is a carry from the Bit 7 to Bit 8 of the result; cleared otherwise.
RS[7] & IMM8[7] | RS[7] & result[7] | IMM8[7] & result[7]
Code and CPU Cycles
Source Form
CMPL RS, #IMM8
Address
Mode
IMM8
11010
Machine Code
RS
IMM8
Cycles
P
MC9S12XDP512 Data Sheet, Rev. 2.21
250
Freescale Semiconductor