MC9S12XD256MAL Datasheet, PDF (637/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

CPU and BDM
Local Memory Map
$0000
$0800
$0C00
$1000
$2000
2K Registers
EEPROM
1K window
1K EEPROM
RAM
4K window
8K RAM
EPAGE
RPAGE
$4000
Unpaged Flash
$8000
Flash
16K window
$C000
Unpaged Flash
$FFFF
Reset Vectors
PPAGE
Chapter 17 Memory Mapping Control (S12XMMCV2)
Global Memory Map
$00_0000
2K Registers
$00_0800
Unimplemented
RAM
$0F_FFFF
RAM
Unimplemented
EEPROM
$13_FFFF
$1F_FFFF
$40_0000
EEPROM
External
Space
Unimplemented
FLASH
FLASH
$7F_FFFF
Figure 17-23. Local to Implemented Global Address Mapping (Without GPAGE)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
637