MC9S12XD256MAL Datasheet, PDF (309/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7
Enhanced Capture Timer (S12ECT16B8CV2)
7.1 Introduction
The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module
enhanced by additional features in order to enlarge the field of applications, in particular for automotive
ABS applications.
This design specification describes the standard timer as well as the additional features.
The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can
be used for many purposes, including input waveform measurements while simultaneously generating an
output waveform. Pulse widths can vary from microseconds to many seconds.
A full access for the counter registers or the input capture/output compare registers will take place in one
clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same
result as accessing them in one word.
7.1.1 Features
• 16-bit buffer register for four input capture (IC) channels.
• Four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered IC
channels. Configurable also as two 16-bit pulse accumulators.
• 16-bit modulus down-counter with 8-bit prescaler.
• Four user-selectable delay counters for input noise immunity increase.
7.1.2 Modes of Operation
• Stop — Timer and modulus counter are off since clocks are stopped.
• Freeze — Timer and modulus counter keep on running, unless the TSFRZ bit in the TSCR1 register
is set to one.
• Wait — Counters keep on running, unless the TSWAI bit in the TSCR1 register is set to one.
• Normal — Timer and modulus counter keep on running, unless the TEN bit in the TSCR1 register
or the MCEN bit in the MCCTL register are cleared.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
309