MC9S12XD256MAL Datasheet, PDF (843/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.25 Port S Data Direction Register (DDRS)
R
W
Reset
7
DDRS7
0
6
DDRS6
5
DDRS5
4
DDRS4
3
DDRS3
2
DDRS2
0
0
0
0
0
Figure 22-27. Port S Data Direction Register (DDRS)
1
DDRS1
0
0
DDRS0
0
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin
is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive
channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
Table 22-27. DDRS Field Descriptions
Field
Description
7–0
DDRS[7:0]
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTS or PTIS registers, when changing the DDRS register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
845