MC9S12XD256MAL Datasheet, PDF (885/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.4.3 Pin Interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same
interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (Figure 22-78) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 22-77 and
Table 22-69).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
t_pign
t_pval
Figure 22-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
Table 22-69. Pulse Detection Criteria
Pulse
STOP
Mode
Unit
STOP¹
Ignored
t_pulse ≤ 3
Bus clocks
t_pulse ≤ t_pign
Uncertain
3 < t_pulse < 4
Bus clocks
t_pign < t_pulse < t_pval
Valid
t_pulse ≥ 4
Bus clocks
t_pulse ≥ t_pval
1 _{These values include the spread of the oscillator frequency over temperature,}
voltage and process.
t_pulse
Figure 22-78. Pulse Illustration
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
887