MC9S12XD256MAL Datasheet, PDF (966/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
open-drain output pins. The CAN4 pins can be re-routed. Refer to Section 23.0.5.37, “Module Routing
Register (MODRR)”.
Port J pins can be used with the routed CAN0 modules. Refer to Section 23.0.5.37, “Module Routing
Register (MODRR)”.
Port J offers 7 I/O pins with edge triggered interrupt capability (Section 23.0.8, “Pin Interrupts”).
NOTE
PJ[5,4,2] are not available in 112-pin packages. PJ[5,4,2,1,0] are not
available in 80-pin packages.
23.0.7.12 Port AD0
This port is associated with the ATD0. Port AD0 pins PAD07–PAD00 can be used for either general
purpose I/O, or with the ATD0 subsystem.
23.0.7.13 Port AD1
This port is associated with the ATD1. Port AD1 pins PAD23–PAD8 can be used for either general
purpose I/O, or with the ATD1 subsystem.
NOTE
PAD[23:16] are not available in 112-pin packages. PAD[23:8] are not
available in 80-pin packages.
23.0.8 Pin Interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same
interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (Figure 23-78) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 23-77 and
Table 23-69).
MC9S12XDP512 Data Sheet, Rev. 2.21
968
Freescale Semiconductor