MC9S12XD256MAL Datasheet, PDF (990/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
Reserved R
0
0
0
0
0
0
0
0
W
PT0AD1 R
PT1AD115 PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110 PT1AD19
W
PT1AD18
PT1AD1 R
PT1AD17
W
PT1AD16
PT1AD15
PT1AD14
PT1AD13
PT1AD12
PT1AD11
PT1AD10
DDR0AD1 R
DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18
W
DDR1AD1 R
DDR1AD17 DDR1AD16 DDR1AD15 DDR1AD14 DDR1AD13 DDR1AD12 DDR1AD11 DDR1AD10
W
RDR0AD1 R
RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110 RDR1AD19 RDR1AD18
W
RDR1AD1 R
RDR1AD17 RDR1AD16 RDR1AD15 RDR1AD14 RDR1AD13 RDR1AD12 RDR1AD11 RDR1AD10
W
PER0AD1 R
PER1AD115 PER1AD114 PER1AD113 PER1AD112 PER1AD111 PER1AD110 PER1AD19 PER1AD18
W
PER1AD1 R
PER1AD17 PER1AD16 PER1AD15 PER1AD14 PER1AD13 PER1AD12 PER1AD11 PER1AD10
W
= Unimplemented or Reserved
Figure 24-2. PIM Register Summary (Sheet 7 of 7)
1. Register implemented, function disabled: Written values can be read back.
24.0.5.1 Port A Data Register (PORTA)
7
6
5
4
3
2
1
0
R
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
W
Reset
0
0
0
0
0
0
0
0
Figure 24-3. Port A Data Register (PORTA)
Read: Anytime.
Write: Anytime.
MC9S12XDP512 Data Sheet, Rev. 2.21
992
Freescale Semiconductor