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MC9S12XD256MAL Datasheet, PDF (32/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 1 Device Overview MC9S12XD-Family
1.1.1 MC9S12XD/B/A Family Features
This section lists the features which are available on
MC9S12XDP512RMV2. See Appendix E Derivative Differences for
availability of features and memory sizes on other family members.
⢠HCS12X Core
â 16-bit HCS12X CPU
â Upward compatible with MC9S12 instruction set
â Interrupt stacking and programmerâs model identical to MC9S12
â Instruction queue
â Enhanced indexed addressing
â Enhanced instruction set
â EBI (external bus interface)
â MMC (module mapping control)
â INT (interrupt controller)
â DBG (debug module to monitor HCS12X CPU and XGATE bus activity)
â BDM (background debug mode)
⢠XGATE (peripheral coprocessor)
â Parallel processing module off loads the CPU by providing high-speed data processing and
transfer
â Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports
⢠PIT (periodic interrupt timer)
â Four timers with independent time-out periods
â Time-out periods selectable between 1 and 224 bus clock cycles
⢠CRG (clock and reset generator)
â Low noise/low power Pierce oscillator
â PLL
â COP watchdog
â Real time interrupt
â Clock monitor
â Fast wake-up from stop mode
⢠Port H & Port J with interrupt functionality
â Digital ï¬ltering
â Programmable rising or falling edge trigger
⢠Memory
â 512, 256 and 128-Kbyte Flash EEPROM
â 4 and 2-Kbyte EEPROM
â 32, 16 and 12-Kbyte RAM
⢠One 16-channel and one 8-channel ADC (analog-to-digital converter)
MC9S12XDP512 Data Sheet, Rev. 2.21
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Freescale Semiconductor
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