MC9S12XD256MAL Datasheet, PDF (786/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 21 External Bus Interface (S12XEBIV2)
21.1.3 Block Diagram
Figure 21-1 is a block diagram of the XEBI with all related I/O signals.
ADDR[22:0]
DATA[15:0]
IVD[15:0]
EWAIT
XEBI
LSTRB
R/W
UDS
LDS
RE
WE
Figure 21-1. XEBI Block Diagram
ACC[2:0]
IQSTAT[3:0]
21.2 External Signal Description
The user is advised to refer to the SoC section for port configuration and location of external bus signals.
NOTE
The following external bus related signals are described in other sections:
CS2, CS1, CS0 (chip selects) — S12X_MMC section
ECLK, ECLKX2 (free-running clocks) — PIM section
TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section
Table 21-1 outlines the pin names and gives a brief description of their function. Refer to the SoC section
and PIM section for reset states of these pins and associated pull-ups or pull-downs.
MC9S12XDP512 Data Sheet, Rev. 2.21
788
Freescale Semiconductor