MC9S12XD256MAL Datasheet, PDF (700/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
Table 19-10. TRANGE Trace Range Encoding
TRANGE
11
Tracing Source
Trace only in range from comparator C to comparator D
Table 19-11. TRCMOD Trace Mode Bit Encoding
TRCMOD
00
01
10
11
Description
NORMAL
LOOP1
DETAIL
Reserved
Table 19-12. TALIGN Trace Alignment Encoding
TALIGN
00
01
10
11
Description
Trigger at end of stored data
Trigger before storing data
Trace buffer entries before and after trigger
Reserved
19.3.1.4 Debug Control Register2 (DBGC2)
0x0023
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
Unimplemented or Reserved
3
2
CDCM
0
0
Figure 19-6. Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 19-13. DBGC2 Field Descriptions
1
0
ABCM
0
0
Field
Description
3–2
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
CDCM[3:2] described in Table 19-14.
1–0
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
ABCM[1:0] described in Table 19-15.
MC9S12XDP512 Data Sheet, Rev. 2.21
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Freescale Semiconductor