MC9S12XD256MAL Datasheet, PDF (826/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 22-5. PORTB Field Descriptions
Field
7–0
PB[7:0]
Description
Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded
modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data
Select (UDS) in normal expanded mode. When this port is not used for external addresses, these pins can be
used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read
returns the value of the port register, otherwise the buffered pin input state is read.
MC9S12XDP512 Data Sheet, Rev. 2.21
828
Freescale Semiconductor