MC9S12XD256MAL Datasheet, PDF (199/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
6.3.1.10 XGATE Register 2 (XGR2)
The XGR2 register (Figure 6-13) provides access to the RISC core’s register 2.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
XGR2
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-13. XGATE Register 2 (XGR2)
Read: In debug mode if unsecured
Write: In debug mode if unsecured
Table 6-10. XGR2 Field Descriptions
Field
Description
15–0
XGATE Register 2 — The RISC core’s register 2
XGR2[15:0]
6.3.1.11 XGATE Register 3 (XGR3)
The XGR3 register (Figure 6-14) provides access to the RISC core’s register 3.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
XGR3
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-14. XGATE Register 3 (XGR3)
Read: In debug mode if unsecured
Write: In debug mode if unsecured
Table 6-11. XGR3 Field Descriptions
Field
Description
15–0
XGATE Register 3 — The RISC core’s register 3
XGR3[15:0]
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
199