MC9S12XD256MAL Datasheet, PDF (883/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.4.2.6 Port T
This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose
I/O, or with the channels of the enhanced capture timer.
22.4.2.7 Port S
This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for general-
purpose I/O, or with the SCI and SPI subsystems.
The SPI0 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”.
NOTE
PS[7:4] are not available in 80-pin packages.
22.4.2.8 Port M
This port is associated with the SCI3, CAN4–0 and SPI0. Port M pins PM[7:0] can be used for either
general purpose I/O, or with the CAN, SCI and SPI subsystems.
The CAN0, CAN4 and SPI0 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register
(MODRR)”.
NOTE
PM[7:6] are not available in 80-pin packages.
22.4.2.9 Port P
This port is associated with the PWM, SPI1 and SPI2. Port P pins PP[7:0] can be used for either general
purpose I/O, or with the PWM and SPI subsystems.
The pins are shared between the PWM channels and the SPI1 and SPI2 modules. If the PWM is enabled
the pins become PWM output channels with the exception of pin 7 which can be PWM input or output. If
SPI1 or SPI2 are enabled and PWM is disabled, the respective pin configuration is determined by status
bits in the SPI modules.
The SPI1 and SPI2 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register
(MODRR)”.
Port P offers 8 I/O pins with edge triggered interrupt capability in wired-OR fashion (Section 22.4.3, “Pin
Interrupts”).
NOTE
PP[6] is not available in 80-pin packages.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
885