MC9S12XD256MAL Datasheet, PDF (151/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.16 ATD Conversion Result Registers (ATDDRx)
The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the
result registers bases on two criteria. First there is left and right justification; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left
justified format. Signed data selected for right justified format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
4.3.2.16.1 Left Justified Result Data
7
R (10-BIT) BIT 9 MSB
R (8-BIT) BIT 7 MSB
6
BIT 8
BIT 6
5
BIT 7
BIT 5
4
BIT 6
BIT 4
3
BIT 5
BIT 3
2
BIT 4
BIT 2
1
BIT 3
BIT 1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-18. Left Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
0
BIT 2
BIT 0
0
7
6
5
4
3
2
1
0
R (10-BIT) BIT 1
BIT 0
0
0
0
0
0
0
R (8-BIT)
u
u
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 4-19. Left Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
151