MC9S12XD256MAL Datasheet, PDF (352/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Bus Clock
P0
P1
P2
P3
P4
P5
P6
P7
352
÷ 1, 2,3, ..., 256
Timer Prescaler
16-Bit Free-Running
16 BITMMaAinINTiTmIMerER
Bus Clock
÷ 1, 2,3, ..., 256
Modulus Prescaler
16-Bit Load Register
16-Bit Modulus
Down Counter
Pin Logic
Delay
Counter
EDG0
8, 12, 16, ..., 1024
Pin Logic
Delay
Counter
EDG1
8, 12, 16, ..., 1024
Pin Logic
Delay
Counter
EDG2
8, 12, 16, ..., 1024
Pin Logic
Delay
Counter
EDG3
8, 12, 16, ..., 1024
Comparator
TC0 Capture/Compare Reg.
TC0H Hold Reg.
Comparator
TC1 Capture/Compare Reg.
TC1H Hold Reg.
Comparator
TC2 Capture/Compare Reg.
TC2H Hold Reg.
Comparator
TC3 Capture/Compare Reg.
TC3H Hold Reg.
0 ^RESET
PAC0
PA0H Hold Reg.
0 ^RESET
PAC1
PA1H Hold Reg.
0 ^RESET
PAC2
PA2H Hold Reg.
0 ^RESET
PAC3
PA3H Hold Reg.
Pin Logic _EDG4
EDG0
SH04
MUX
Pin Logic _EDG5
EDG1
SH15
MUX
Comparator
TC4 Capture/Compare Reg.
ICLAT, LATQ, BUFEN
(Force Latch)
Comparator
TC5 Capture/Compare Reg.
Write 0x0000
to Modulus Counter
Pin Logic _EDG6
EDG2
MUX
SH26
Comparator
TC6 Capture/Compare Reg.
LATQ
(MDC Latch Enable)
Pin Logic _EDG7
EDG3
SH37
MUX
Comparator
TC7 Capture/Compare Reg.
Figure 7-66. Detailed Timer Block Diagram in Latch Mode when PRNT = 1
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor