MC9S12XD256MAL Datasheet, PDF (622/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.3.2.4 Direct Page Register (DIRECT)
Address: 0x0011
R
W
Reset
7
DP15
0
6
DP14
0
5
DP13
0
4
DP12
0
3
DP11
0
2
DP10
0
1
DP9
0
0
DP8
0
Figure 17-8. Direct Register (DIRECT)
Read: Anytime
Write: anytime in special modes, one time only in other modes.
This register determines the position of the direct page within the memory map.
Table 17-8. DIRECT Field Descriptions
Field
7–0
DP[15:8]
Description
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct
addressing mode. The bits from this register form bits [15:8] of the address (see Figure 1-9).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
Bit22
Bit16 Bit15
Bit8 Bit7
Bit0
DP [15:8]
CPU Address [15:0]
Figure 17-9. DIRECT Address Mapping
Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global
instruction in direct addressing mode or by the appropriate local address to the global address expansion
(refer to Expansion of the CPU Local Address Map).
Example 17-2. This example demonstrates usage of the Direct Addressing Mode by a global instruction
LDAADR
MOVB
MOVB
GLDAA
EQU $0000
#$80,DIRECT
#$14,GPAGE
<LDAADR
;Initialize LDADDR with the value of $0000
;Initialize DIRECT register with the value of $80
;Initialize GPAGE register with the value of $14
;Load Accu A from the global address $14_8000
MC9S12XDP512 Data Sheet, Rev. 2.21
622
Freescale Semiconductor