MC9S12XD256MAL Datasheet, PDF (444/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 10-22. CANIDMR0–CANIDMR3 Register Field Descriptions
Field
Description
7:0
AM[7:0]
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
Module Base + 0x001C (CANIDMR4)
0x001D (CANIDMR5)
0x001E (CANIDMR6)
0x001F (CANIDMR7)
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
1
AM1
0
0
AM0
0
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
1
AM1
0
0
AM0
0
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
1
AM1
0
0
AM0
0
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
1
AM1
0
0
AM0
0
Figure 10-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
MC9S12XDP512 Data Sheet, Rev. 2.21
444
Freescale Semiconductor