MC9S12XD256MAL Datasheet, PDF (794/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 21 External Bus Interface (S12XEBIV2)
The following terminology is used:
‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins
‘x’ — Undefined output pin values
‘z’ — Tristate pins
‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’
21.4.2.2.1 Read Access Timing
Table 21-9. Read Access (1 Cycle)
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0] ...
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0] ...
DATA[15:0] (internal read) ...
DATA[15:0] (external read) ...
R/W
...
Access #0
1
2
high
low
high
low
acc 0
acc 1
addr 0 iqstat -1 addr 1 iqstat 0
?
ivd 0
?
z
z
z
?
z
data 0
z
1
1
1
1
Access #1
3
...
high
low ...
acc 2 ...
addr 2 iqstat 1 ...
ivd 1 ...
z
z ...
data 1
z ...
1
1 ...
Table 21-10. Read Access (2 Cycles)
Access #0
Access #1
Bus cycle ->
...
1
2
3
...
ECLK phase
... high
low
high
low
high
low ...
ADDR[22:20] / ACC[2:0] ...
acc 0
000
acc 1 ...
ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat-1 addr 0 iqstat 0 addr 1 0000 ...
ADDR[15:0] / IVD[15:0] ...
?
x
ivd 0 ...
DATA[15:0] (internal read) ... ?
z
z
z
z
z ...
DATA[15:0] (external read) ... ?
z
z
z
data 0
z ...
R/W
... 1
1
1
1
1
1 ...
Table 21-11. Read Access (n–1 Cycles)
Access #0
Access #1
Bus cycle ->
...
1
2
3
...
n
...
ECLK phase
... high
low
high
low
high
low ... high
low ...
ADDR[22:20] / ACC[2:0] ...
acc 0
000
000 ...
acc 1 ...
ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat-1 addr 0 iqstat 0 addr 0 0000 ... addr 1 0000 ...
ADDR[15:0] / IVD[15:0] ...
?
x
x ...
ivd 0 ...
DATA[15:0] (internal read) ... ?
z
z
z
z
z ... z
z ...
DATA[15:0] (external read) ... ?
z
z
z
z
z ... data 0
z ...
R/W
... 1
1
1
1
1
1 ... 1
1 ...
MC9S12XDP512 Data Sheet, Rev. 2.21
796
Freescale Semiconductor