MC9S12XD256MAL Datasheet, PDF (952/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-52. DDRJ Field Descriptions
Field
Description
7–0
DDRJ[7:4]
DDRJ[2:0]
Data Direction Port J
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTJ or PTIJ registers, when changing the DDRJ register.
23.0.5.57 Port J Reduced Drive Register (RDRJ)
R
W
Reset
7
RDRJ7
0
6
5
4
3
2
0
RDRJ6
RDRJ5
RDRJ4
RDRJ2
0
0
0
0
0
= Unimplemented or Reserved
Figure 23-59. Port J Reduced Drive Register (RDRJ)
1
RDRJ1
0
0
RDRJ0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 23-53. RDRJ Field Descriptions
Field
Description
7–0
Reduced Drive Port J
RDRJ[7:4] 0 Full drive strength at output.
RDRJ[2:0] 1 Associated pin drives at about 1/6 of the full drive strength.
23.0.5.58 Port J Pull Device Enable Register (PERJ)
R
W
Reset
7
PERJ7
1
Read: Anytime.
Write: Anytime.
6
5
4
3
2
0
PERJ6
PERJ5
PERJ4
PERJ2
1
1
1
0
1
= Unimplemented or Reserved
Figure 23-60. Port J Pull Device Enable Register (PERJ)
1
PERJ1
1
0
PERJ0
1
MC9S12XDP512 Data Sheet, Rev. 2.21
954
Freescale Semiconductor