MC9S12XD256MAL Datasheet, PDF (825/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

22.3.2.1 Port A Data Register (PORTA)
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
R
W
Alt.
Function
Reset
7
PA7
ADDR15
mux
IVD15
0
6
5
4
3
2
PA6
PA5
PA4
PA3
PA2
ADDR14
mux
IVD14
ADDR13
mux
IVD13
ADDR12
mux
IVD12
ADDR11
mux
IVD11
ADDR10
mux
IVD10
0
0
0
0
0
Figure 22-3. Port A Data Register (PORTA)
1
PA1
ADDR9
mux
IVD9
0
0
PA0
ADDR8
mux
IVD8
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 22-4. PORTA Field Descriptions
Field
7–0
PA[7:0]
Description
Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively in
expanded modes. When this port is not used for external addresses, these pins can be used as general purpose
I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
22.3.2.2 Port B Data Register (PORTB)
R
W
Alt.
Function
7
PB7
ADDR7
mux
IVD7
Reset
0
6
PB6
5
PB5
4
PB4
3
PB3
2
PB2
ADDR6
mux
IVD6
ADDR5
mux
IVD5
ADDR4
mux
IVD4
ADDR3
mux
IVD3
ADDR2
mux
IVD2
0
0
0
0
0
Figure 22-4. Port B Data Register (PORTB)
1
PB1
ADDR1
mux
IVD1
0
0
PB0
ADDR0
mux
IVD0
or
UDS
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
827