MC9S12XD256MAL Datasheet, PDF (992/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.4 Port B Data Direction Register (DDRB)
R
W
Reset
7
DDRB7
0
6
DDRB6
5
DDRB5
4
DDRB4
3
DDRB3
2
DDRB2
0
0
0
0
0
Figure 24-6. Port B Data Direction Register (DDRB)
1
DDRB1
0
0
DDRB0
0
Read: Anytime.
Write: Anytime.
Table 24-7. DDRB Field Descriptions
Field
Description
7–0
DDRB[7:0]
Data Direction Port B — This register controls the data direction for port B. DDRB determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTB after changing the DDRB register.
24.0.5.5 Port E Data Register (PORTE)
R
W
Alt.
Func.
Reset
7
PE7
XCLKS
or
ECLKX2
0
6
PE6
MODB
0
5
PE5
MODA
0
4
PE4
3
PE3
2
PE2
ECLK
EROMCTL
0
0
0
1
PE1
0
PE0
IRQ
XIRQ
—¹
—¹
= Unimplemented or Reserved
Figure 24-7. Port E Data Register (PORTE)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Anytime.
MC9S12XDP512 Data Sheet, Rev. 2.21
994
Freescale Semiconductor