MC9S12XD256MAL Datasheet, PDF (1133/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
27.4.2.2.1 Data Compress Operation
The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to
generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for
simultaneous compression, then the signature from each Flash block is further compressed to generate a
single 16-bit signature. The final 16-bit signature, found in the FDATA registers after the data compress
operation has completed, is based on the following logic equation which is executed on every data
compression cycle during the operation:
MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0]
Eqn. 27-1
where MISR is the content of the internal signature register associated with each Flash block and DATA
is the data to be compressed as shown in Figure 27-27.
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[15]
+ DQ + DQ + DQ + DQ + DQ + DQ
...
M0
M1
M2
M3
M4
M5
>
>
>
>
>
>
+ DQ
M15
>
+
+ = Exclusive-OR
MISR[15:0] = Q[15:0]
+
+
Figure 27-27. 16-Bit MISR Diagram
During the data compress operation, the following steps are executed:
1. MISR for each Flash block is reset to 0xFFFF.
2. Initialized DATA equal to 0xFFFF is compressed into the MISR for each selected Flash block
which results in the MISR containing 0x0001.
3. DATA equal to the selected Flash array data range is read and compressed into the MISR for each
selected Flash block with addresses incrementing.
4. DATA equal to the selected Flash array data range is read and compressed into the MISR for each
selected Flash block with addresses decrementing.
5. If Flash block 0 is selected for compression, DATA equal to the contents of the MISR for Flash
block 0 is compressed into the MISR for Flash block 0. If data in Flash block 0 was not selected
for compression, the MISR for Flash block 0 contains 0xFFFF.
6. If Flash block 1 is selected for compression, DATA equal to the contents of the MISR for Flash
block 1 is compressed into the MISR for Flash block 0.
7. If Flash block 2 is selected for compression, DATA equal to the contents of the MISR for Flash
block 2 is compressed into the MISR for Flash block 0.
8. If Flash block 3 is selected for compression, DATA equal to the contents of the MISR for Flash
block 3 is compressed into the MISR for Flash block 0.
9. The contents of the MISR for Flash block 0 are written to the FDATA registers.
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
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