MC9S12XD256MAL Datasheet, PDF (853/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

22.3.2.38 Port P Data Register (PTP)
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
R
W
PWM
SPI
Reset
7
PTP7
PWM7
SCK2
0
6
PTP6
5
PTP5
4
PTP4
3
PTP3
2
PTP2
PWM6
SS2
0
PWM5
PWM4
PWM3
PWM2
MOSI2
MISO2
SS1
SCK1
0
0
0
0
Figure 22-40. Port P Data Register (PTP)
1
PTP1
PWM1
MOSI1
0
0
PTP0
PWM0
MISO1
0
Read: Anytime.
Write: Anytime.
Port P pins 7, and 5–0 are associated with the PWM as well as the SPI1 and SPI2 modules. These pins can
be used as general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
The PWM function takes precedence over the general purpose I/O and the SPI2 or SPI1 function if the
associated PWM channel is enabled. While channels 6 and 5-0 are output only if the respective channel is
enabled, channel 7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM section
for details.
The SPI2 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section
for details.
The SPI1 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section
for details.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
855